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final publication# 11419 rev: e amendment/ 0 issue date: may 1998 am27c64 64 kilobit (8 k x 8-bit) cmos eprom distinctive characteristics n fast access time speed options as fast as 45 ns n low power consumption 20 a typical cmos standby current n jedec-approved pinout n single +5 v power supply n 10% power supply tolerance standard n 100% flashrite? programming typical programming time of 1 second n latch-up protected to 100 ma from C1 v to v cc + 1 v n high noise immunity n versatile features for simple interfacing both cmos and ttl input/output compatibility two line control functions n standard 28-pin dip, pdip, and 32-pin plcc packages general description the am27c64 is a 64-kbit, ultraviolet erasable pro- grammable read-only memory. it is organized as 8k words by 8 bits per word, operates from a single +5 v supply, has a static standby mode, and features fast single address location programming. products are available in windowed ceramic dip packages, as well as plastic one time programmable (otp) pdip and plcc packages. data can be typically accessed in less than 45 ns, al- lowing high-performance microprocessors to operate without any wait states. the device offers separate output enable (oe#) and chip enable (ce#) controls, thus eliminating bus contention in a multiple bus micro- processor system. amds cmos process technology provides high speed, low power, and high noise immunity. typical power consumption is only 80 mw in active mode, and 100 w in standby mode. all signals are ttl levels, including programming sig- nals. bit locations may be programmed singly, in blocks, or at random. the device supports amds flashrite programming algorithm (100 s pulses), re- sulting in a typical programming time of 1 second. block diagram 11419e-1 a0Ca12 address inputs pgm# ce# oe# v cc v ss v pp data outputs dq0Cdq7 output buffers y gating 65,538 bit cell matrix x decoder y decoder output enable chip enable and prog logic
2 am27c64 product selector guide connection diagrams top view dip plcc notes: 1. jedec nomenclature is in parenthesis. 2. dont use (du) for plcc. pin designations a0Ca12 = address inputs ce# (e#) = chip enable input dq0Cdq7 = data input/outputs oe# (g#) = output enable input pgm# (p#) = program enable input v cc =v cc supply voltage v pp = program voltage input v ss = ground nc = no internal connection logic symbol family part number am27c64 speed options v cc = 5.0 v 5% -255 v cc = 5.0 v 10% -45 -55 -70 -90 -120 -150 -200 max access time (ns) 45 55 70 90 120 150 200 250 ce# (e#) access (ns) 45 55 70 90 120 150 200 250 oe# (g#) access (ns) 30 35 40 40 50 50 50 50 3 4 5 2 1 9 10 11 12 13 23 22 21 20 19 7 8 18 17 6 28 27 16 14 26 25 24 15 a6 a5 a4 a3 a2 a1 a0 dq0 a7 dq1 dq2 v ss a8 a9 a11 oe# (g#) a10 ce# (e#) dq7 v cc pgm# (p#) dq6 nc dq5 dq4 dq3 v pp a12 11419e-2 dq5 du dq4 dq3 du 13130 2 3 4 5 6 7 8 9 10 11 12 13 17 18 19 20 16 15 14 29 28 27 26 25 24 23 22 21 32 a6 a5 a4 a3 a2 a1 a0 nc dq0 a8 a9 a11 nc oe# (g#) a10 ce# (e#) dq7 dq6 a7 a12 v pp v cc pgm# (p#) nc dq1 dq2 v ss 11419e-3 13 8 dq0Cdq7 a0Ca12 ce# (e#) pmg# (p#) oe# (g#) 11419e-4
am27c64 3 ordering information uv eprom products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. device number/description am27c64 64 kilobit (8 k x 8-bit) cmos uv eprom am27c64 -45 d c optional processing blank = standard processing b = burn-in temperature range c = commercial (0 c to +70 c) i= industrial (C40 c to +85 c) e = extended (C55 c to +125 c) package type d = 28-pin ceramic dip (cdv028) speed option see product selector guide and valid combinations b valid combinations am27c64-45 dc, dcb, di, dib am27c64-55 am27c64-70 dc, dcb, di, dib, de, deb am27c64-90 am27c64-120 am27c64-150 am27c64-200 am27c64-255 v cc = 5.0 v 5% dc, dcb, di, dib
4 am27c64 ordering information otp eprom products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. device number/description am27c64 64 kilobit (8 k x 8-bit) cmos otp eprom am27c64 -55 p c optional processing blank = standard processing temperature range c = commercial (0 c to +70 c) i= industrial (C40 c to +85 c) e = extended (C55 c to +125 c) package type p = 28-pin plastic dip (pd 028) j = 32-pin plastic leaded chip carrier (pl 032) speed option see product selector guide and valid combinations valid combinations am27c64-55 jc, pc, ji, pi am27c64-70 am27c64-90 am27c64-120 am27c64-150 am27c64-200 am27c64-255
am27c64 5 functional description device erasure in order to clear all locations of their programmed con- tents, the device must be exposed to an ultraviolet light source. a dosage of 15 w seconds/cm 2 is required to completely erase the device. this dosage can be ob- tained by exposure to an ultraviolet lampwavelength of 2537 ?with intensity of 12,000 w/cm 2 for 15 to 20 minutes. the device should be directly under and about one inch from the source, and all filters should be re- moved from the uv light source prior to erasure. note that all uv erasable devices will erase with light sources having wavelengths shorter than 4000 ?, such as fluorescent light and sunlight. although the erasure process happens over a much longer time period, ex- posure to any light source should be prevented for maximum system reliability. simply cover the package window with an opaque label or substance. device programming upon delivery, or after each erasure, the device has all of its bits in the one, or high state. zeros are loaded into the device through the programming pro- cedure. the device enters the programming mode when 12.75 v 0.25 v is applied to the v pp pin, and ce# and pgm# are at v il . for programming, the data to be programmed is ap- plied 8 bits in parallel to the data pins. the flowchart in the programming section of the eprom products data book (section 5, figure 5-1) shows amds flashrite algorithm. the flashrite algo- rithm reduces programming time by using a 100 s pro- gramming pulse and by giving each address only as many pulses to reliably program the data. after each pulse is applied to a given address, the data in that ad- dress is verified. if the data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. this process is repeated while se- quencing through each address of the device. this part of the algorithm is done at v cc = 6.25 v to assure that each eprom bit is programmed to a sufficiently high threshold voltage. after the final address is completed, the entire eprom memory is verified at v cc = v pp = 5.25 v. please refer to section 5 of the eprom products data book for additional programming information and spec- ifications. program inhibit programming different data to multiple devices in par- allel is easily accomplished. except for ce#, all like in- puts of the devices may be common. a ttl low-level program pulse applied to one devices ce# input with v pp = 12.75 v 0.25 v and pgm# low will program that particular device. a high-level ce# input inhibits the other devices from being programmed. program verify a verification should be performed on the programmed bits to determine that they were correctly programmed. the verify should be performed with oe# and ce#, at v il , pgm# at v ih , and v pp between 12.5 v and 13.0 v. autoselect mode the autoselect mode provides manufacturer and de- vice identification through identifier codes on dq0C dq7. this mode is primarily intended for programming equipment to automatically match a device to be pro- grammed with its corresponding programming algo- rithm. this mode is functional in the 25 c 5 c ambient temperature range that is required when pro- gramming the device. to activate this mode, the programming equipment must force v h on address line a9. two identifier bytes may then be sequenced from the device outputs by tog- gling address line a0 from v il to v ih (that is, changing the address from 00h to 01h). all other address lines must be held at v il during the autoselect mode. byte 0 (a0 = v il ) represents the manufacturer code, and byte 1 (a0 = v ih ), the device identifier code. both codes have odd parity, with dq7 as the parity bit. read mode to obtain data at the device outputs, chip enable (ce#) and output enable (oe#) must be driven low. ce# con- trols the power to the device and is typically used to se- lect the device. oe# enables the device to output data, independent of device selection. addresses must be stable for at least t acc Ct oe . refer to the switching waveforms section for the timing diagram. standby mode the device enters the cmos standby mode when ce# is at v cc 0.3 v. maximum v cc current is reduced to 100 a. the device enters the ttl-standby mode when ce# is at v ih . maximum v cc current is reduced to 1.0 ma. when in either standby mode, the device places its outputs in a high-impedance state, indepen- dent of the oe# input. output or-tieing to accommodate multiple memory connections, a two-line control function provides: n low memory power dissipation, and n assurance that output bus contention will not occur. ce# should be decoded and used as the primary de- vice-selecting function, while oe# be made a common
6 am27c64 connection to all devices in the array and connected to the read line from the system control bus. this as- sures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular mem- ory device. system applications during the switch between active and standby condi- tions, transient current peaks are produced on the ris- ing and falling edges of chip enable. the magnitude of these transient current peaks is dependent on the out- put capacitance loading of the device. at a minimum, a 0.1 f ceramic capacitor (high frequency, low inherent inductance) should be used on each device between v cc and v ss to minimize transient effects. in addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on eprom ar- rays, a 4.7 f bulk electrolytic capacitor should be used between v cc and v ss for each eight devices. the loca- tion of the capacitor should be close to where the power supply is connected to the array. mode select table notes: 1. v h = 12.0 v 0.5 v. 2. x = either v ih or v il . 3. a1Ca8 and a10C12 = v il . 4. see dc programming characteristics for v pp voltage during programming. mode ce# oe# pgm# a0 a9 v pp outputs read v il v il xxx xd out output disable x v ih x x x x high z standby (ttl) v ih x x x x x high z standby (cmos) v cc 0.3 v x x x x x high z program v il xv il xxv pp d in program verify v il v il v ih xxv pp d out program inhibit v ih xxxxv pp high z autoselect (note 3) manufacturer code v il v il xv il v h x01h device code v il v il xv ih v h x15h
am27c64 7 absolute maximum ratings storage temperature otp products. . . . . . . . . . . . . . . . . . C65 c to +125 c all other products . . . . . . . . . . . . . . C65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . C55 c to +125 c voltage with respect to v ss all pins except a9, v pp , v cc . . C0.6 v to v cc + 0.6 v a9 and v pp (note 2) . . . . . . . . . . . . . C0.6 v to 13.5 v v cc (note 1). . . . . . . . . . . . . . . . . . . . . C0.6 v to 7.0 v notes: 1. minimum dc voltage on input or i/o pins C0.5 v. during voltage transitions, the input may overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input and i/o pins is v cc + 5 v. during voltage transitions, input and i/o pins may overshoot to v cc + 2.0 v for periods up to 20ns. 2. minimum dc input voltage on a9 is C0.5 v. during voltage transitions, a9 and v pp may overshoot v ss to C2.0 v for periods of up to 20 ns. a9 and v pp must not exceed+13.5 v at any time. stresses above those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure of the device to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . . . .0 c to +70 c industrial (i) devices ambient temperature (t a ) . . . . . . . . . C40 c to +85 c extended (e) devices ambient temperature (t a ) . . . . . . . .C55 c to +125 c supply read voltages v cc for 5% devices . . . . . . . . . . +4.75 v to +5.25 v v cc for 10% devices . . . . . . . . . +4.50 v to +5.50 v operating ranges define those limits between which the func- tionality of the device is guaranteed.
8 am27c64 dc characteristics over operating range (unless otherwise specified) caution : the device must not be removed from (or inserted into) a socket when v cc or v pp is applied. notes: 1. v cc must be applied simultaneously or before v pp , and removed simultaneously or after v pp .. 2. i cc1 is tested with oe# = v ih to simulate open outputs. 3. minimum dc input voltage is C0.5 v. during transitions, the inputs may overshoot to C2.0 v for periods less than 20 ns. maximum dc voltage on output pins is v cc + 0.5 v, which may overshoot to v cc + 2.0 v for periods less than 20 ns. figure 1. typical supply current vs. frequency v cc = 5.5 v, t = 25 c figure 2. typical supply current vs. temperature v cc = 5.5 v, f = 10 mhz parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C400 a 2.4 v v ol output low voltage i ol = 2.1 ma 0.45 v v ih input high voltage 2.0 v cc + 0.5 v v il input low voltage C0.5 +0.8 v i li input load current v in = 0 v to v cc 1.0 a i lo output leakage current v out = 0 v to v cc c/i devices 1.0 a e devices 5.0 i cc1 v cc active current (note 2) ce# = v il , f = 10 mhz, i out = 0 ma 25 ma i cc2 v cc ttl standby current ce# = v ih 1.0 ma i cc3 v cc cmos standby current ce# = v cc 0.3 v 100 a i pp1 v pp supply current (read) ce# = oe# = v il , v pp = v cc 100 a 11419e-5 12345678910 30 25 20 15 10 frequency in mhz supply current in ma 11419e-6 C75 C50 C55 0 25 50 75 100 125 150 30 25 20 15 10 temperature in c supply current in ma
am27c64 9 test conditions table 1. test specifications switching test waveform key to switching waveforms 2.7 k w c l 6.2 k w 5.0 v device under te s t 11419e-7 figure 3. test setup note: diodes are in3064 or equivalents. test condition -45, -55, -70 all others unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 20 ns input pulse levels 0.0C3.0 0.45C2.4 v input timing measurement reference levels 1.5 0.8, 2.0 v output timing measurement reference levels 1.5 0.8, 2.0 v 2.4 v 0.45 v input output test points 2.0 v 2.0 v 0.8 v 0.8 v 11419e-8 3 v 0 v input output 1.5 v 1.5 v test points note: for c l = 100 pf. note: for c l = 30 pf. ks000010-pal waveform inputs outputs steady changing from h to l changing from l to h dont care, any change permitted changing, state unknown does not apply center line is high impedance state (high z)
10 am27c64 ac characteristics caution: do not remove the device from (or insert it into) a socket or board that has v pp or v cc applied. notes: 1. v cc must be applied simultaneously or before v pp , and removed simultaneously or after v pp . 2. this parameter is sampled and not 100% tested. 3. switching characteristics are over operating range, unless otherwise specified. 4. see figure 3 and table 1 for test specifications. switching waveforms notes: 1. oe# may be delayed up to t acc C t oe after the falling edge of the addresses without impact on t acc . 2. t df is specified from oe# or ce#, whichever occurs first. package capacitance notes: 1. this parameter is only sampled and not 100% tested. 2. t a = +25 c, f = 1 mhz. parameter symbols description test setup am27c64 unit jedec standard -45 -55 -70 -90 -120 -150 -200 -255 t avqv t acc address to output delay ce#, oe# = v il max 45 55 70 90 120 150 200 250 ns t elqv t ce chip enable to output delay oe# = v il max 45 55 70 90 120 150 200 250 ns t glqv t oe output enable to output delay ce# = v il max3035404050505050 ns t ehqz t ghqz t df (note 2) chip enable high or output enable high to output high z, whichever occurs first max2525252530303030 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min00000000ns addresses ce# oe# output 11419e-9 addresses valid high z high z t ce valid output 2.4 0.45 2.0 0.8 2.0 0.8 t acc (note 1) t oe t df (note 2) t oh parameter symbol parameter description test conditions cdv028 pl 032 pd 028 unit typ max typ max typ max c in input capacitance v in = 0 810610510pf c out output capacitance v out = 0 1114 8 12 8 10pf
am27c64 11 physical dimensions* cdv02828-pin ceramic dual in-line package, uv lens (measured in inches) * for reference only. bsc is an ansi standard for basic space centering. pd 02828-pin plastic dual in-line package (measured in inches) top view side view end view index and terminal no. 1 i.d. area .565 .605 1.435 1.490 .005 min .045 .065 .014 .026 .100 bsc .015 .060 .160 .220 .125 .200 base plane seating plane .300 bsc .600 bsc .008 .018 94 105 .700 max 16-000038h-3 cdv028 df10 3-30-95 ae datum d center plane datum d center plane 1 uv lens pin 1 i.d. 1.440 1.480 .530 .580 .005 min .045 .065 .090 .110 .140 .225 .120 .160 .014 .022 seating plane .015 .060 .630 .700 0 10 .600 .625 16-038-sb-ag pd 028 dg75 7-13-95 ae 28 15 14 .008 .015
12 am27c64 physical dimensions pl 03232-pin plastic leaded chip carrier (measured in inches) revision summary for am27c64 revision e global changed formatting to match current data sheets. trademarks copyright ? 1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. flashrite is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies . .050 ref. .026 .032 top view pin 1 i.d. .485 .495 .447 .453 .585 .595 .547 .553 16-038fpo-5 pl 032 da79 6-28-94 ae side view seating plane .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 ref. .490 .530

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